1. Field of the Invention
The present invention generally relates to multipliers and, more particularly, is directed to a serial input multiplier apparatus in which a series of digital data serially input and a predetermined coefficient are multiplied to output a series of multiplied result in a digital signal processing apparatus.
2. Description of the Prior Art
There are known multiplying circuits that calculate a product of an input data word I consisting of n bits that are received sequentially and a pre-determined coefficient C also consisting of a plurality of bits. Assuming that the word length of the coefficient C is 7 bits, for example, then the input data word I and the coefficient C are expressed as follows where the most significant bit (MSB) is expressed in the left-hand side: EQU I=(In-1, In-2, . . . , IO), EQU C=(C6, C5, . . . , CO)
In that case, a product 0 of the input data word I and the coefficient C can be expressed as follows: EQU O=(On+6, On+5, . . . , O1, O0)
The multiplication for calculating this product O is achieved by the addition of partial products as shown in FIG. 1.
FIG. 2 shows in block form a conventional multiplying circuit which is used to execute the calculation shown in FIG. 1.
Referring to FIG. 2, processing units 1A, 1B, 1C, . . . all having the same arrangement are supplied with data Ik, Ik+1, Ik+2, . . . representing respective bits of the input data word I and output data Ok, Ok+1, Ok+2, . . . of respective bits of the product O. The processing unit 1A, for example, comprises seven full adders 2A through 2G and seven AND gates 3A through 3G. Data C0 to C6 of the coefficient C are respectively supplied to one input terminal of the AND gates 3A through 3G and data Ik is commonly supplied to the other input terminal of the AND gates 3A through 3G. The full adders 2A through 2F are respectively supplied at their input portions with the outputs of the AND gates 3A through 3F, sum outputs of the processing units of the preceding stage and carry outputs. The full adder 2G for the most significant digit is supplied at its input portion with an output of the AND gate 3G, data "0" and a carry output of the most significant digit from the processing unit of the preceding stage.
Further, the multiplying circuit of FIG. 2 is constructed by the repetition of the processing unit 1A so that, if the processing unit IA is used in a time division manner, then the multiplying circuit can be miniaturized. If the processing unit is utilized in a time division fashion, then respective bits of the input data I are serially input and respective bits of the product O which are the multiplied result are output serially.
FIG. 3 shows in block form a conventional multiplying circuit which inputs and outputs data serially in one such time division fashion. In FIG. 3, like parts corresponding to those of FIG. 2 are marked with the same references and therefore need not be described in detail. In this multiplying circuit shown in FIG. 3, data C0 to C6 representing respective bits of the coefficient C are respectively supplied to one input terminal of the AND gates 3A through 3G and outputs of the AND gates 3A through 3G are respectively supplied to one input terminal of the full adders 2A through 2G. The other input terminals of the AND gates 3A through 3G are commonly connected to an input terminal 4 and a sum output terminal of the full adder 2A of the least significant digit is connected to an output terminal 7. Carry outputs of the full adders 2A through 2G are respectively fed through one clock delay registers 5A through 5G back to the other input terminals of the same adder and sum outputs of the full adders 2B through 2G are respectively supplied through one clock delay registers 6B through 6G to the remaining input terminals of the full adders 2A through 2F for the next lower digit. The multiplying circuit shown in FIG. 3 is described, for example, in page 62 and FIG. 4.2 of "APPLICATION OF DIGITAL SIGNAL PROCESSING" written by Nobuo Inoue and published by the Institute of Electronics and Communication Engineers of Japan.
In the example of FIG. 3, from the input terminal 4 respective bits Ii of input data word word I are supplied in the sequential order of I0 in the first cycle, I1 in the second cycle, . . . , In-1 in the n'th cycle to the AND gates 3A through 3G and respective bits of product O are output from the output terminal 7 in the sequential order of O0 in the first cycle, O1 in the second cycle, . . . , On+6 in the (n+7)'th cycle. To be more concrete, if the coefficient C is set as follows: ##EQU1## then the circuit shown in FIG. 3 is simplified and becomes equivalent to a circuit shown in FIG. 4. More specifically, in the circuit shown in FIG. 4, although the respective input terminals of the full adders 2A, 2C, 2F and 2G of digits in which the bit Ci of the coefficient C is "1" in the circuit of FIG. 3 are connected to the input terminal 4, the respective input terminals of the full adders 2B, 2D and 2E of digits in which the bit Ci of the coefficient C is "0" are not connected to the input terminal 4.
Accordingly, although the four full adders 2A, 2C, 2F and 2G execute useful processing for adding bit Ii of input data word I supplied thereto through the input terminal 4, the remaining three full adders 2B, 2D and 2E perform useless processing for adding "0" instead of adding data Ii representing respective bits of the input data word I.
In order to generalize the aforementioned fact, assuming that the coefficient C is m bits and that ml bits of "1" and m2 (m2=m-m1) bits of "0" exist among the bits Ci of the coefficient C, then it is to be noted that m2 full adders out of m full adders within the circuit of FIG. 4 perform useless processing. If the full adders, which do not perform useful processing, are removed, then the circuit scale of the multiplying circuit can be miniaturized more and the multiplying circuit can be made more inexpensive.
Further, the above-mentioned multiplying circuit needs a calculation time corresponding to the number of cycles equal to the word length of the resultant product.
More specifically, assuming that the word length of input data words I, J, K, . . . is 6 bits and that the word length of the coefficient C is 6 bits, then the word length of the products O, P, Q, . . . is 12 bits. Therefore, the input data word I, the coefficient C and the product O can be expressed in a binary numeral fashion as follows where the bit (MSB) of the most significant digit is provided on the left-hand side. EQU I=(I5, I4, I3, I2, I1, I0) EQU C=(C5, C4, C3, C2, C1, C0) EQU O=I.times.C=(O11, O10, O9, . . . , O1, O0) (1)
Similarly, input data word J can be expressed as (J5, J4, . . . , J0) and product P also can be expressed as (P11, P10, . . . , P1, P0). Therefore, input data words and products will hereinafter be expressed in a binary numeral fashion.
In that case, according to the prior art, respective bits of input data words I, J, . . . , must be supplied in a format so that a dummy bit formed of six "0", is interposed therebetween as shown in FIG. 5A. The reason for this will be described below. That is, since the conventional multiplying circuit for multiplying the numbers of word length of 6 bits is formed such that six full adders are connected in series via delay circuits, after an MSB of an input data word I is input to the leftmost full adder, a time period of six cycles is needed before a calculated result is output to the output terminal through the delay circuits, full adders provided on the right of the delay circuit, etc. Therefore, the next data cannot be input during that period. This conventional multiplying circuit generates at its output terminal respective bits such as O, P or the like sequentially in response to FIG. 5A as shown in FIG. 5B.
However, the dummy bits must be inserted between input data I, J or the like as shown in FIG. 5A and there is then the disadvantage such that a signal line (bus) for transmitting input data cannot be utilized effectively. Furthermore, although the data rate of the input data is the same as the very time of the calculation in such multiplying circuit, the insertion of the dummy bits increases the calculation time considerably.